To date, multiple system vendors have converged around Class 3-based solutions (Figure 1), recently announcing their next generation offerings. This industry convergence creates the benefit of economies of scale and broad industry investments into the technology used in this baud rate class, the same class being used for 800G MSA pluggable solutions.

Figure 1.  Acacia and other coherent vendors have announced Class 3 Terabit Era solutions.

Advancements Resulting in 65% Power-per-Bit Savings Over Current Competing Solutions
Doubling the baud rate from Class 2 to Class 3 in silicon was a significant engineering achievement, combining design advancements in high-speed Radio Frequency (RF) and Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) components plus well-designed co-packaging integration of silicon and silicon photonic (SiPh) components. These achievements led to Acacia’s successful 140Gbaud in-house capability that is being leveraged in the commercially available CIM 8 solution.

With high-volume shipments of multiple coherent Class 2 module products utilizing Acacia’s 3D Siliconization, this proven co-packaging integration solution provided the foundation for extending this capability to Class 3 140Gbaud implementation utilized in the CIM 8 (Figure 2). 3D Siliconization maximizes signal integrity by co-packaging all high-speed components including the coherent Digital Signal Processor (DSP) application-specific integrated circuit (ASIC), transmitter and receiver silicon photonics, and 3D stacked RF components into a single device that is manufactured in a standard electronics packaging house. Silicon technology has demonstrated cost and power advantages over alternative technologies, making it the material system of choice for these higher baud rates. These advancements enabling a doubling of the baud rate have led to a 65% power-per-bit savings of CIM 8 over current competing solutions that utilize alternative optical material systems. In addition, the size and power savings of this latest generation enabled the ability to house this 1.2T 140Gbaud solution in a pluggable form-factor.

Figure 2.  An example of 3D Siliconization used in the CIM 8 module, resulting in a volume electronics manufacturable high-speed single device larger than a quarter.

2^nd Generation 3D Shaping Advances Coherent Performance
The CIM 8 is powered by Jannu, Acacia’s 8^th generation coherent DSP ASIC. The design greatly expands on the success of the Pico DSP ASIC predecessor used in the widely deployed performance-optimized Class 2 AC1200 module (Figure 1). The AC1200 was the first module to introduce 3D Shaping, which provided finely tunable Adaptive Baud Rate up to 70Gbaud as well as finely tunable modulation up to 6 bits/symbol. The AC1200 had achieved record breaking spectral efficiency at the time of its introduction, as evidenced by a subsea trial over the MAREA submarine cable connecting Virginia Beach, Virginia to the city of Bilbao in Spain. Finely tunable baud rate helps maximize spectral efficiency in any given passband channel, converting excess margin into additional capacity/reach, and avoids wasted bandwidth due to network fragmentation.

Figure 3.  A popular feature is the fine-tunability of baud rate introduced by Acacia with the Class 2 AC1200; CIM 8 incorporates the same Adaptive Baud feature (as part of 2^nd Generation 3D Shaping) for Class 3 baud rate tunability.

The 5nm Jannu DSP ASIC in CIM 8 intelligently optimizes optical transmission using 2^nd Generation 3D Shaping with an increased Adaptive Baud Rate tunable range up to 140Gbaud, as well as finely tunable modulation up to 6 bits/symbol using enhanced Probabilistic Constellation Shaping (PCS). With 2^nd Generation 3D Shaping, the CIM 8 module can achieve a 20% improvement in spectral efficiency.

Terabit Era Solutions Provide Full Network Coverage
Class 3 technology not only ushers in the terabit era, but also enables full multi-haul network coverage as the high baud rate capabilities transport nx400GbE client traffic across a service provider’s entire network. Full network coverage is not only enabled by adjustment of the modulation, but also implies the capability to optimize for various network conditions which include overcoming transmission impairments.

Figure 4. CIM 8 1.2T, 1T, 800G, and 400G transmission constellations operating at Class 3 baud rates providing wide network coverage addressing multiple applications.

CIM 8 offers significant power-per-bit reductions as well as cost efficiencies for various optical network transport applications.

DCI/Metro Reaches
For transporting 3x400GbE or 12x100GbE client traffic with metro reaches in a single carrier, the CIM 8 is tuned to ~6 bits/symbol (equivalent to 64QAM, example constellation on left). Data center interconnect (DCI) applications would take advantage of this high-capacity 1.2T transport capability to tie data center locations together. This amounts to 38.4T per C-band fiber capacity.

Long-Haul Reaches

For transporting 2x400GbE with long-haul reaches, the CIM 8 is tuned to ~4 bits/symbol (equivalent to 16QAM, example constellation on the right). Wide 800G network coverage is achieved with the Class 3 140Gbaud capabilities enabling service providers to provide end-to-end 2x400GbE, 8x100GbE, or native 800GbE transport across their networks, covering essentially all terrestrial applications.

Ultra-Long-Haul/Subsea Reaches

And for ultra-long-haul/subsea reaches, the CIM 8 is tuned to ~2 bits/symbol (equivalent to QPSK, example constellation on the left). As with the previous scenarios, spectral efficiency with a wavelength channel is optimized by fine-tuning of the baud rate. These high spectrally efficient modes can carry mixed 100GbE and 400GbE traffic over the longest subsea routes in the world with lowest cost per bit. It’s worth noting that almost a decade ago, Acacia demonstrated SiPh capabilities for subsea coherent deployments. CIM 8 incorporates second generation non-linear equalization (NLEQ) capabilities to mitigate the non-linear effects of optical transmission especially for these ultra-long-haul/subsea links providing additional OSNR.

In all the above scenarios, the CIM 8 utilizes advanced power-efficient algorithms to compensate for chromatic and polarization dependent dispersion. In addition, the module accounts for coverage of aerial fiber network segments that require fast state-of-polarization (SOP) tracking and recovery due to lightning strikes. The SOP tracking speed of CIM 8 is double the speed of its predecessor. This fast SOP tracking feature can also be utilized for sensing applications.

Network Operators Achieve Record Breaking Field Trials with CIM 8
CIM 8 capabilities have already been put to the test as illustrated by multiple record breaking field trials across a wide range of applications. These include >5600km 400G transmission over a mobile carrier’s backbone network, 2200km 800G transmission over a research and education network, and >540km 1T transmission over a wholesale carrier’s network.

Acacia continues to demonstrate its technology leadership by leveraging mature knowledge in proven silicon-based coherent technology, producing the first shipping coherent solution to lead the industry into the Terabit Era with the 1.2T pluggable CIM 8 module. With the breakthrough capability of 140Gbaud transmission along with the advanced Jannu DSP ASIC using 2^nd Gen 3D Shaping and leveraging 3D Siliconization, network operators can support full network coverage for multi-haul applications, especially to support growing demands for nx400GbE and upcoming 800GbE traffic.

References:
Blog: Terabit Today: Maximize Network Coverage
Blog: How Industry Trends are Driving Coherent Technology Classifications
Blog Series: The Road Ahead for Next-Generation Multi-Haul Designs Part 1, Part 2, Part 3

 Over the last 10 years, we’ve seen rapid increases in capacity per wavelength by increasing modulation order from QPSK to 16QAM to 64QAM, as well as increasing baud rate supported by opto-electronic devices. However, beyond the coherent modulation order of 64QAM, the achievable performance isn’t sufficient to address target applications due to the reduction in reach.  As a result, increasing baud rates has been looked to as the primary means of increasing capacity per wavelength.  This requires innovative and cost-effective implementations to provide higher baud rate solutions and packaging advancements.  Opto-electronic integration and co-packaging are techniques that were discussed by Acacia’s Founder and Chief Technology Officer Benny Mikkelsen in his OFC 2019 Plenary talk and continue to be critical to support the ever-increasing need for higher data rates and smaller, cost-effective optical interfaces for cloud, access, and transport applications.

Opto-Electronic Integration and Co-Packaging Explained
These techniques are used to reduce components in size and power while also increasing functionality and performance of the solution. Opto-electronic integration generally refers to the process of integrating a wide range of optical functions on a single chip, such as the large amount of optical and opto-electronic functions being achieved in a photonic integrated circuit (PIC). While co-packaging is the ability to combine multiple chips into a single package which can be further integrated into a transceiver module. The main benefit is that it can then be manufactured as if it’s a single component with even more functions.

Opto-electronic integration, particularly through silicon photonics, enables the miniaturization of coherent transceivers. The benefits of opto-electronic integration can be seen in the below graphic, which shows how the size of a coherent transceiver was reduced significantly over a few product generations.  By leveraging these techniques, each new generation was able to raise the bar to increase capacity while reducing power and size.

Figure 1. Opto-electronic integration and co-packaging have enabled coherent transceivers to become significantly smaller over the last decade.

Three Main Benefits of Opto-electronic Integration and Co-Packaging

1. Reduced Power

It takes a massive amount of power to operate data centers, which is why sustainability ranks top on data center operator’s agendas. Opto-electronic integration and advanced packaging helps lower the power consumption of the coherent modules used for moving data across networks.

The benefit of having multiple devices packaged into one compact component means fewer interfaces and the ability to support higher speeds per lane. Electrical compensation of PCB routed high-speed signals, which consumes power, is essentially eliminated.  As an example, by co-design and co-packaging the trans-impedance amplifier (TIA) and driver chips with the silicon photonics-based PIC on the same substrate as the digital signal processor (DSP) ASIC, the DAC termination can be eliminated and can result in a 35 percent DAC power reduction.

Figure 2. Co-design and co-packaging of the TIA and driver chips with the silicon photonics-based PIC on the same substrate as the DSP ASIC eliminates the DAC termination and can result in a 35% DAC power reduction.

2. Reduced Size

Silicon Photonics
Using silicon as an optical medium and leveraging CMOS fabrication processing technology, silicon photonics allows tighter monolithic integration of many optical functions within a single device. While traditional optics systems used many discrete devices, silicon photonics allows all those devices to fit onto a single silicon chip reducing the size.  Silicon photonics has been a key enabler for achieving the tremendous size reduction in Figure 1.

Component Stacking
In component stacking, the DSP and PIC are tightly co-packaged on the same substrate, and the high-speed modulator driver and TIA components are stacked on the PIC which also reduces the size.  Component stacking is a process widely adopted in the electronics manufacturing process that is now being applied to opto-electronic technology manufacturing.

Co-packaging and Integrated Control IC
Size reductions are achieved by integrating functions and the control IC through co-packaging techniques. Smaller devices can translate into either more functionality within the same form factor and power consumption footprint or a smaller form factor with the same functionality and power consumption as the previous generation. For example, in the Acacia CFP2 form factor, the integration of multiple discrete control ICs into one integrated device led to a 500 percent reduction in board footprint.

3. Increased Capacity

Enhancing DSP and Increasing Baud Rate
With network capacity demands increasing, network operators are challenged with an ongoing need to deploy solutions that can keep up with these capacity demands while being power, size and cost efficient. High speed opto-electronic integration and advanced packaging can deliver high-capacity transport from the state-of-art DSP.

Increasing baud rate has always been an efficient way to enable more cost-effective optical networks by reducing the number of optics required to support a given transmission capacity. By doubling baud rate over previous generations, we can support twice the capacity per carrier over greater reaches than prior generations. This approach provides a simple, scalable path that supports higher capacity per carrier over the reaches needed for existing and new network architectures.

Acacia’s Implementation: 3D Siliconization
Acacia’s approach to co-packaging is called 3D Siliconization technology. This process utilizes highly scalable and reliable volume electronics manufacturing processes which applies 3D stacking packaging techniques to enable a single device to include all the high speed opto-electronic functions necessary for coherent transceivers. With 3D Siliconization, the high-speed RF interfaces are tightly coupled together, resulting in improved signal integrity for high baud rate signals.

Figure 3.  3D Siliconization improves signal integrity and performance via the reduction of electrical inter-connects, in addition to the benefits in cost, reliability, power, and size.

This device decreases footprint by including the DSP, PIC, drivers, and TIAs, and is manufactured using standard CMOS packaging processes that leverage the same reliability, cost, and volume scaling advantages.  This approach is utilized by Acacia’s 400G pluggable family and the 1.2T 140Gbaud Coherent Interconnect Module 8 (CIM 8).